EFLAGS bit name description 0 Carry Flag Set when an arithmetic operation generates a carry or a borrow. Provides an overflow indication for unsigned arithmetic. 1 (undefined) Always set to 1 2 Parity Flag Set when the parity of the lower 8 bits of the result is even. 3 (undefined) Always set to 0 4 Auxiliary Flag Set when an arithmetic operation generates a carry or a borrow out of bit 3. This is used in performing Binary Coded Decimal operations. 5 (undefined) Always set to 0 6 Zero Flag Set when the result of an operation is 0. 7 Sign Flag Set to the most significant bit of the result of an operation. The most significant bit is the sign bit in two's complement notation. 8 Trap Flag (1) A single-step interrupt will occur after every instruction. (0) Normal instruction execution ** Note: Trap Flag is always cleared when an interrupt is generated either by software or hardware. 9 Interrupt Flag (1) Enables the recognition of external interrupts. (0) External interrupts are held pending. 10 Direction Flag (1) String instructions post-decrement the string index register after each step. (0) String instructions post-increment the string index register after each step. 11 Overflow Flag Set if the result of an arithmetic operation is too large or too small to be represented as a two's complement integer in the number of bits available to store the result 12|I/O Privilege Level Supports protection model. Indicates the 13| privilege level required to perform I/O instructions. If the current privilege level is numerically less than or equal to the IOPL, I/O intructions can be executed. 14 Nested Task Flag (1) Controls operation of IRET instruction. The IRET (interrupt return) instruction will return through a task switch to the task indicated in the current TSS. (0) A normal return is performed by restoring EFLAGS, CS and EIP with values from the stack 15 (undefined) Always set to 0 16 Restart Flag (1) Indicates that debug faults should be ignored. (0) Debug faults are accepted. ** Note: this bit is cleared by the processor at the successful completion of every instruction, and is set when a fault other than a debug fault is signalled. 17 Virtual Mode Flag (1) Processor will execute this task in Virtual 8086 mode. (0) Processor will execute this task in normal protected mode. 18 Alignment Check (1) Processor will generate an Alignment Check Fault whenever a memory reference is made from privilege level 3 to a misaligned address. A misaligned address is defined as any data reference that is not evenly divisible by its size. (0) Processor operates normal; it does not generate faults on misaligned addresses. ** 486 and higher only ** 19 Virtual Interrupt Flag (1) Virtualizes Interrupt flag when Virtual 8086 Mode Extensions or Protected Mode Extensions are enabled. When set indicates that interrupts are handled as usual. (0) Indicates that current task should not receive external interrupts. If an interrupt is generated while this flag is clear then a protected mode exception is generated. ** Virtual or Protected Mode Extensions Supported Only ** 20 Virtual Interrupt Pending This bit is used by the operating system to indicate to the processor that a virtualized interrupt is pending for the current task. If set, then any attempt to toggle the Virtual Interrupt Flag to the on state will generate a protected mode exception. ** Virtual or Protected Mode Extensions Supported Only ** 21 ID Flag if this bit can be toggled then the processor supports the CPUID instruction. 22 (undefined) Always set to 0 23 (undefined) Always set to 0 24 (undefined) Always set to 0 25 (undefined) Always set to 0 26 (undefined) Always set to 0 27 (undefined) Always set to 0 28 (undefined) Always set to 0 29 (undefined) Always set to 0 30 (undefined) Always set to 0 31 (undefined) Always set to 0 CPUID Results (EAX = 0) CPU Indentification ** CPUID instruction only available if ID Flag of EFLAGS register can be toggled EAX = Highest Supported Function of CPUID instruction (largest value of EAX when CPUID instruction is executed that will produce a meaningful result) EBX:EDX:ECX = Vendor ID String "GenuineIntel" = Intel processor (i486 or later processor) "CyrixInstead" = Cyrix processor (Cyrix 6x86 or later processor) "AuthenticAMD" = AMD processor (AMD 486 or later processor) "NexGenDriven" = NexGen processor (NexGen Nx586 or later processor) "UMC UMC UMC " = UMC processor (UMC U5S or later processor) CPUID Results (EAX = 1) Get Chip Type and Supported Features ** CPUID instruction only available if ID Flag of EFLAGS register can be toggled ** Function 1 is only valid if a previous call to CPUID with Function 0 returned EAX greater than or equal to 1. ** Never try modifying a bit in Control Register 4 coresponding to a feature which is not supported. EAX = Chip Type bit name description 0|Minor Stepping Indicates the family's revision number 1| Notes: 5.0V iPentium processors before step #7 have a 2| documented bug in the fdiv instruction 3| 3.0V iPentium processors before step #4 have the same bug. See Appendix A for listings of many steppings 4|Major Stepping Indicates the family's model number 5| Values for Intel 486 Family: 6| 0000 = i486DX 7| 0001 = i486DX50 0010 = i486SX 0011 = i486DX/2 0100 = i486SL 0101 = i486SX/2 0111 = i486DX/2 WB 1000 = i486DX/4 1001 = i486DX/4 WB Values for AMD 486 Family: 0011 = AMD 486DX/2 0111 = AMD 486DX/2 WB 1000 = AMD 486DX/4 1001 = AMD 486DX/4 WB 1110 = AMD X5WT 1111 = AMD X5WB Values for UMC 486 Family: 0001 = Cyrix U5D 0010 = Cyrix U5S Values for Intel Pentium Family: 0000 = iPentium 5.0V 60/66Mhz A-stepping 0001 = iPentium 5.0V 60/66Mhz 0010 = iPentium 3.3V 75/90/100/120/133Mhz (iP54) 0011 = iPentium P24T 0100 = iPentium Overdrive for iPentium 3.3V chips 0110 = iPentium Overdrive for iPentium 5.0V chips Values for Cyrix Pentium-compatible Family: 1001 = Cyrix 5x86 Values for AMD Pentium-compatible Family: 0000 = AMD SSA5 0001 = AMD 5k86 Values for NexGen Pentium-compatible Family: 0000 = Late-model NexGen Nx586 or Nx586FPU Values for iPentiumPro Family: 0000 = iPentiumPro A-stepping 0001 = iPentiumPro 0100 = iPentiumPro P55CT (iP54 socket OverDrive) Values for Cyrix PentiumPro-compatible Family: 0010 = Cyrix 6x86 0011 = Cyrix 6x86 8|Family Indicates which family of Intel processors 9| the chip is comprable to. 10| 0100 = i486 11| 0101 = iPentium 0110 = iPentiumPro 12|Model Indicates whether processor is original OEM 13| processor, an Overdrive processor, or a dual processor (capable of being used in a dual- processor system) 00 = Original OEM processor 01 = Overdrive processor 10 = dual processor 14 (reserved) 15 (reserved) 16 (reserved) 17 (reserved) 18 (reserved) 19 (reserved) 20 (reserved) 21 (reserved) 22 (reserved) 23 (reserved) 24 (reserved) 25 (reserved) 26 (reserved) 27 (reserved) 28 (reserved) 29 (reserved) 30 (reserved) 31 (reserved) EBX:ECX = (undefined) EDX = Supported Features bit name description 0 FPU (1) Processor contains a built-in FPU which supports the i387 instruction set. (0) Processor does not contain an on-chip FPU supporting the i387 instruction set, although a math coprocessor may be present. 1 Virtual Mode Enhancements (1) Virtual Mode Enhancements are supported and may be toggled via bit 0 in Control Register 4. (0) Virtual Mode Enhancements are not supported. 2 Debugging Extensions (1) Debugging Extensions are supported and may be toggled via bit 3 in Control Register 4. (0) Debugging Extensions are not supported. 3 Page Size Extension (1) The Page Size Extension is supported and may be toggled via bit 4 in Control Register 4. (0) The Page Size Extension is not supported. 4 Time Stamp Counter (1) The RDTSC (Read Time Stamp Counter) instruction is supported and access may be controlled via bit 2 in Control Register 4. (0) The RDTSC (Read Time Stamp Counter) instruction is not supported. 5 Model Specific Registers (1) Model Specific Registers are implemented with RDMSR (Read Model Specific Register) and WRMSR (Write Model Specific Register) instructions. (0) Model Specific Registers are not supported. 6 Physical Address Extension(1) Physical Addresses larger than 32-bit are supported. (0) Physical Addresses are limited to 32 bits. 7 Machine Check Exception (1) Machine Check Exception (#12h) is supported and may be enabled or disabled by toggling bit 6 of Control Register 4. (0) Machine Check Exception (#12h) is not supported. 8 Compare and Exchange (1) The CMPXCHG8 (Compare and exchange 8 bytes) instruction is supported. (0) The CMPXCHG8 (Compare and exchange 8 bytes) instruction is not supported. 9 Local APIC (1) The processor contains a local APIC (Advanced Programmable Interrupt Controller) (0) The processor does not contain a local APIC, instead relying on an external Programmable Interrupt Controller. 10 (reserved) 11 (reserved) 12 Memory Type Range (1) Memory Type Range Registers supported. (0) Memory Type Range Registers are not supported. 13 Page Global Enable (1) Page Global Enable supported. (0) Page Global Enable not supported. 14 Machine Check Architecture 15 Conditional Move (1) Conditional Move instructions (CMOVxx, FCMOVxx, and FCOMI) are supported. (0) Conditional Move instructions are not supported. 16 (reserved) 17 (reserved) 18 (reserved) 19 (reserved) 20 (reserved) 21 (reserved) 22 (reserved) 23 MMX (1) 'Multimedia' instruction set supported. (0) 'Multimedia' instruction set not supported. 24 (reserved) 25 (reserved) 26 (reserved) 27 (reserved) 28 (reserved) 29 (reserved) 30 (reserved) 31 (reserved) CPUID Results (EAX = 2) Get Cache Configuration Descriptors ** CPUID instruction only available if ID Flag of EFLAGS register can be toggled ** Function 2 is only valid if a previous call to CPUID with Function 0 returned EAX greater than or equal to 2. EAX,EBX,ECX,EDX = Cache Descriptors (8 bits each, packed end to end) The lowest 8 bits of EAX (AL) contain the values 00000001, other values are reserved for future use. The remainder of EAX as well as EBX, ECX, and EDX all contain valid 8 bit descriptors. Valid descriptors may be identified because the most significant bit of the 8 bit descriptor is set to 0. The following is a list of current descriptor values and their respective cache characteristics: descriptor value description 00000000 unused (NULL descriptor) 00000001 code TLB, 4K pages, 4-way set associative, 64 entries 00000010 code TLB, 4M pages, 4-way set associative, 4 entries 00000011 data TLB, 4K pages, 4-way set associative, 64 entries 00000100 data TLB, 4M pages, 4-way set associative, 8 entries 00000110 instruction cache, 8K, 4-way set associative, 32-byte lines 00001100 data cache, 8K, 4-way set associative, 32-byte lines 01000001 code/data cache, 128K, 4-way set associative, 32-byte lines 01000010 code/data cache, 256K, 4-way set associative, 32-byte lines 01000011 code/data cache, 512K, 4-way set associative, 32-byte lines CR0 (Control Register) bit name description 0 Protection Enable (1) Processor is in protected mode (0) Processor is in real mode 1 Math Present (1) The WAIT instruction will raise a Device Not Available exception is the Task Switched flag is set. (0) The WAIT instruction operates as normal. 2 Emulate (1) Floating point instructions will raise a Device Not Available exception. (0) Floating point instructions will be sent directly to the processor. ** Note: the WAIT instruction ignores the setting of this bit and is controlled solely by the Math Present bit. 3 Task Switched Set whenever a task switch occurs. While set, any floating point instruction will generate an exception before it is executed. A WAIT instruction will generate an exception also only if the Math Present bit is also set. 4 Extension Type (1) Math Coprocessor is a 387 or later part (32-bit) (0) Math Coprocessor is a 287 part ( 16-bit) or is not present. **Note: this bit is set by the processor whenever it is reset and should not be changed by software. 5 (undefined) Always set to 0 6 (undefined) Always set to 0 7 (undefined) Always set to 0 8 (undefined) Always set to 0 9 (undefined) Always set to 0 10 (undefined) Always set to 0 11 (undefined) Always set to 0 12 (undefined) Always set to 0 13 (undefined) Always set to 0 14 (undefined) Always set to 0 15 (undefined) Always set to 0 16 (undefined) Always set to 0 17 (undefined) Always set to 0 18 (undefined) Always set to 0 19 (undefined) Always set to 0 20 (undefined) Always set to 0 21 (undefined) Always set to 0 22 (undefined) Always set to 0 23 (undefined) Always set to 0 24 (undefined) Always set to 0 25 (undefined) Always set to 0 26 (undefined) Always set to 0 27 (undefined) Always set to 0 28 (undefined) Always set to 0 29 (undefined) Always set to 0 30 (undefined) Always set to 0 31 Paging Enable (1) Linear addresses are translated to physical addresses by the processor's paging mechanism. (0) Linear addresses are directly mapped to physical addresses. CR2 (Control Register) Used to report linear address which caused paging exception. CR3 (Control Register) bit name description 0 (undefined) Always set to 0 1 (undefined) Always set to 0 2 (undefined) Always set to 0 3 Page Write Through 4 Page Cache Disable 5 (undefined) Always set to 0 6 (undefined) Always set to 0 7 (undefined) Always set to 0 8 (undefined) Always set to 0 9 (undefined) Always set to 0 10 (undefined) Always set to 0 11 (undefined) Always set to 0 12|Page Directory Base Page (4K) granular physical address of the Page 13| Directory, The Page Directory controls the entire 14| paging mechanism for the translation of linear 15| addresses to physical addresses. 16| 17| 18| 19| 20| 21| 22| 23| 24| 25| 26| 27| 28| 29| 30| 31| CR4 (Control Register) ** Only available on processors as noted in the CPUID instruction description. Coresponding flag in CPUID features flag should be checked before toggling any bit in the CR4. bit name description 0 Virtual Mode Extensions (1) Virtual8086 Mode Extensions are enabled. See description of Virtual8086 Mode Extensions for details. (0) Virtual8086 Mode behaves as defined for a 80386. 1 Virtual Interrupts (1) Protected Mode Virtual Interrupts are enabled. While this bit is set and the task's current privilege level is outside the task's I/O privilege level and instructions which modify the Interrupt Flag actually modify the Virtual Interrupt Flag. (0) Protected Mode interrupts are not virtualized and therefore do actually modify the Interrupt Flag. 2 Time Stamp Disable (1) Read Time Stamp Counter instruction is a privileged instruction that may only be executed if current privilege level is 0 without causing a protection fault. (0) Read Time Stamp Counter instruction is not a privileged instruction and therefore can be executed at any privilege level. 3 Debugging Extensions (1) Debugging Extensions are enabled. I/O breakpoints may be defined and Debug Registers 4 and 5 are protected. See description of Debug Registers for details. (0) Debugging Extensions are disabled. Processor-level debug support behaves as defined for a 80386; Debug Registers 4 and 5 are aliases of Debug Registers 6 and 7 respectively and I/O breakpoints cannot be set. 4 Page Size Extension (1) The Page Size Extension is enabled. If the Page Size flag of a Page Directory Entry is set then the entry describes a 4M page. If the Page Size flag of a Page Directory Entry is clear then the entry is a table of up to 1024 Page Table Entries each of which describing a 4K page. (0) The Page Size Extension is disabled and Page lookups are performed as defined for a 80386. Setting the Page Size flag of a Page Directory generates a protection fault. 5 Physical Address Extension(1) Processor support for 36-bit physical address space and related paging mechanisms are enabled. See description of Page Address Extensions for details. (0) Processor can only access 32 bits of address space as defined for a 80386. 6 Machine Check Exception (1) A Machine Check Exception is generated whenever a fatal system error is detected such as failed memory parity check. (0) No exception is generated. 7 Page Global Extensions (1) Reloading CR3 (the Page Directory Base) clears all entries from the Translation Look-aside Buffer, the processor's internal caching mechanism for Page Table Entries, except for Page Eable Entries or Page Directory Entries with the Global flag set. (0) Reloading CR3 clears all entries from the Translation Look-aside Buffer as defined for a 80386. 8 Performance Counter (1) Read Performance Counter instruction is a privileged instruction that may only be executed if current privilege level is 0 without causing a protection fault. (0) Read Performance Counter instruction is not a privileged instruction and therefore can be executed at any privilege level. 9 (undefined) Always set to 0 10 (undefined) Always set to 0 11 (undefined) Always set to 0 12 (undefined) Always set to 0 13 (undefined) Always set to 0 14 (undefined) Always set to 0 15 (undefined) Always set to 0 16 (undefined) Always set to 0 17 (undefined) Always set to 0 18 (undefined) Always set to 0 19 (undefined) Always set to 0 20 (undefined) Always set to 0 21 (undefined) Always set to 0 22 (undefined) Always set to 0 23 (undefined) Always set to 0 24 (undefined) Always set to 0 25 (undefined) Always set to 0 26 (undefined) Always set to 0 27 (undefined) Always set to 0 28 (undefined) Always set to 0 29 (undefined) Always set to 0 30 (undefined) Always set to 0 31 (undefined) Always set to 0 DR0-3 (Debug Breakpoint Registers) Contain the linear address associated with each of the four breakpoint conditions. Additional breakpoint qualifiers are located in DR7. DR6 (Debug Status Register) ** The processor never clears any bits in register DR6. If DR7 indicates that an exception should be generated for a given condifion, the handler has the responsibility to clear DR6 before terminating so that future exceptions can properly detect the cause. In addition it should be noted that the breakpoint detected flags will be set whether an exception is generated for the condition or not; it is then also the responsibility of the debug exception handler to ignore any breakpoint detected flags coresponding to breakpoints not specifically enabled by DR7. (The same is true for the Debug Protection flag) bit name description 0 Breakpoint(0) Detected (1) Processor sets this bit to indicate that the breakpoint condition specified by breakpoint linear address register DR0 was detected. ** Note: this bit is set even if the breakpoint condition has not been specifically enabled by DR7 (0) The breakpoint condition indicated by DR0 has not been detected. 1 Breakpoint(1) Detected (1) Processor sets this bit to indicate that the breakpoint condition specified by breakpoint linear address register DR1 was detected. ** Note: this bit is set even if the breakpoint condition has not been specifically enabled by DR7 (0) The breakpoint condition indicated by DR1 has not been detected. 2 Breakpoint(2) Detected (1) Processor sets this bit to indicate that the breakpoint condition specified by breakpoint linear address register DR2 was detected. ** Note: this bit is set even if the breakpoint condition has not been specifically enabled by DR7 (0) The breakpoint condition indicated by DR2 has not been detected. 3 Breakpoint(3) Detected (1) Processor sets this bit to indicate that the breakpoint condition specified by breakpoint linear address register DR3 was detected. ** Note: this bit is set even if the breakpoint condition has not been specifically enabled by DR7 (0) The breakpoint condition indicated by DR3 has not been detected. 4 (undefined) Always set to 0 5 (undefined) Always set to 0 6 (undefined) Always set to 0 7 (undefined) Always set to 0 8 (undefined) Always set to 0 9 (undefined) Always set to 0 10 (undefined) Always set to 0 11 (undefined) Always set to 0 12 (undefined) Always set to 0 13 Debug Protection (1) Processor sets this bit to indicate that the next instruction to be executed will read or write to a debug register. ** Note: this bit is set even if Debug Protection is not enabled in DR7 (0) Next instruction does not attempt to modify a debug register. 14 Single Step (1) Processor sets this bit if the program enters the debug exception handler because of a single-step condition. The single-step condition is enabled by the Trap Flag bit in the EFLAGS register. (0) Debug exception was not triggered by a single-step trap. 15 Task Switch Breakpoint (1) Processor sets this bit if the program enters the debug exception handler because a task switched occurred to a task with the Debug Trap bit in its TSS enabled. (0) Debug exception was not triggered by a task switch to a task with its Debug Trap bit enabled. 16 (undefined) Always set to 0 17 (undefined) Always set to 0 18 (undefined) Always set to 0 19 (undefined) Always set to 0 20 (undefined) Always set to 0 21 (undefined) Always set to 0 22 (undefined) Always set to 0 23 (undefined) Always set to 0 24 (undefined) Always set to 0 25 (undefined) Always set to 0 26 (undefined) Always set to 0 27 (undefined) Always set to 0 28 (undefined) Always set to 0 29 (undefined) Always set to 0 30 (undefined) Always set to 0 31 (undefined) Always set to 0 DR7 (Debug Control Register) bit name description 0 Local Breakpoint(0) Always set to 0 1 Global Breakpoint(0) Always set to 0 2 Local Breakpoint(1) Always set to 0 3 Global Breakpoint(1) Always set to 0 4 Local Breakpoint(2) Always set to 0 5 Global Breakpoint(2) Always set to 0 6 Local Breakpoint(3) Always set to 0 7 Global Breakpoint(3) Always set to 0 8 Local Breakpoint Enable (1) Processor will slow execution such that data breakpoints are reported on exactly the instruction which causes them. (0) Processor will run at full speed and may get slightly ahead of the reporting of the breakpoint conditions on instructions that perform data writes near the end of their execution. ** Note: The processor automatically clears this flag whenever a task switch occurs. 9 Global Breakpoint Enable (1) Processor will slow execution such that data breakpoints are reported on exactly the instruction which causes them. (0) Processor will run at full speed and may get slightly ahead of the reporting of the breakpoint conditions on instructions that perform data writes near the end of their execution. 10 (undefined) Always set to 0 11 (undefined) Always set to 0 12 (undefined) Always set to 0 13 Debug Protection Enable (1) Enables the debug register protection condition which is reported by the Debug Protection bit of DR6. Any attempt to modify the debug registers will generate a debug exception which can be detected by testing the Debug Protection bit of DR6. (0) Disables the debug register protection condition. Software may freely modify the state of any of the debug registers. ** Note: The processor automatically clears this flag on entry to the debug exception handler allowing it free access to the debug registers. 14 (undefined) Always set to 0 15 (undefined) Always set to 0 16|Breakpoint(0) Condition Condition which triggers breakpoint 0. If either 17| the Local Breakpoint(0) or the Global Breakpoint(0) bits are set then an exception will be generated whenever this condition is met. Values for breakpoint conditions are: 00 = Instruction execution only 01 = Data writes only 10 = If Debugging Extensions are enabled in CR4, I/O reads and writes; If Debugging Extensions are disabled or not supported, undefined. 11 = Data reads and writes 18|Breakpoint(0) Length Always set to 0 19| 20|Breakpoint(1) Condition Always set to 0 21| 22|Breakpoint(1) Length Always set to 0 23| 24|Breakpoint(2) Condition Always set to 0 25| 26|Breakpoint(2) Length Always set to 0 27| 28|Breakpoint(3) Condition Always set to 0 29| 30|Breakpoint(3) Length Always set to 0 31| =============================================================================== Appendix A - Stepping Values for various processors As returned by CPUID instruction Intel iPentium P5 processor: type family model step mask clock SX-no Vcc in V øC note 0 5 1 3 B1 50/50 Q0399 4.75-5.25 85 #1,#2 0 5 1 3 B1 60/60 Q0352 4.75-5.25 85 #1 0 5 1 3 B1 60/60 Q0400 4.75-5.25 75 #1,#2 0 5 1 3 B1 60/60 Q0394 4.75-5.25 80 #2,#3 0 5 1 3 B1 66/66 Q0353 4.90-5.25 75 #1 0 5 1 3 B1 66/66 Q0395 4.90-5.25 70 #2,#3 0 5 1 3 B1 60/60 Q0412 4.75-5.25 85 #1 0 5 1 3 B1 60/60 SX753 4.75-5.25 85 #1 0 5 1 3 B1 66/66 Q0413 4.90-5.40 75 #1 0 5 1 3 B1 66/66 SX754 4.90-5.40 75 #1,#4 0 5 1 5 C1 60/60 Q0466 4.75-5.25 80 #3 0 5 1 5 C1 60/60 SX835 4.75-5.25 80 #3 0 5 1 5 C1 60/60 SZ949 4.75-5.25 80 #3,#5 0 5 1 5 C1 66/66 Q0467 4.90-5.40 70 #3 0 5 1 5 C1 66/66 SX837 4.90-5.40 70 #3 0 5 1 5 C1 66/66 SZ950 4.90-5.40 70 #3,#5 0 5 1 7 D1 60/60 Q0625 4.75-5.25 80 #3 0 5 1 7 D1 60/60 SX948 4.75-5.25 80 #3 0 5 1 7 D1 60/60 SX974 5.15-5.40 70 #3 0 5 1 7 D1 60/60 ----- 4.75-5.25 80 #3,#5,#6 0 5 1 7 D1 66/66 Q0626 4.90-5.40 70 #3 0 5 1 7 D1 66/66 SX950 4.90-5.40 70 #3 0 5 1 7 D1 66/66 Q0627 5.15-5.40 70 #3 0 5 1 7 D1 66/66 SX949 5.15-5.40 70 #3 0 5 1 7 D1 66/66 ----- 4.90-5.40 70 #3,#5,#6 Notes: #1 = non-heat spreader package #2 = engineering samples only #3 = heat spreader package #4 = 66 MHz B1 shipped after work week 34 of 1993 were tested to Vcc=4.90-5.40V #5 = boxed iPentium processor #6 = not marked with a S-spec number Intel iPentium P54 processor: type family model step mask clock SX-no comment 0 5 2 1 B1 75/50 Q0540 ES 0 5 2 1 B1 75/50 Q0541 ES 0 5 2 1 B1 90/60 Q0542 STD 0 5 2 1 B1 90/60 Q0613 VR 0 5 2 1 B1 90/60 Q0543 DP 0 5 2 1 B1 100/66 Q0563 STD 0 5 2 1 B1 100/66 Q0587 VR 0 5 2 1 B1 100/66 Q0614 VR 0 5 2 1 B1 75/50 Q0601 TCP 0 5 2 1 B1 90/60 SX879 STD 0 5 2 1 B1 90/60 SX885 MD 0 5 2 1 B1 90/60 SX909 VR 0 5 2 1 B1 90/60 SX874 DP,STD 0 5 2 1 B1 100/66 SX886 MD 0 5 2 1 B1 100/66 SX910 VR,MD 0 5 2 2 B3 90/60 Q0628 STD 0/2 5 2 2 B3 90/60 Q0611 STD 0/2 5 2 2 B3 90/60 Q0612 VR 0 5 2 2 B3 100/66 Q0677 VRE,MD 0 5 2 2 B3 75/50 Q0606 TCP 0 5 2 2 B3 75/50 SX951 TCP 0 5 2 2 B3 90/60 SX923 STD 0 5 2 2 B3 90/60 SX922 VR 0 5 2 2 B3 90/60 SX921 MD 2 5 2 2 B3 90/60 SX942 DP,STD 2 5 2 2 B3 90/60 SX943 DP,VR 2 5 2 2 B3 90/60 SX944 DP,MD 0 5 2 2 B3 90/50 SZ951 STD,#5 0 5 2 2 B3 100/66 SX960 VRE,MD 0/2 5 2 4 B5 75/50 Q0704 TCP 0/2 5 2 4 B5 75/50 Q0666 STD 0/2 5 2 4 B5 90/60 Q0653 STD 0/2 5 2 4 B5 90/60 Q0654 VR 0/2 5 2 4 B5 90/60 Q0655 MD 0/2 5 2 4 B5 100/66 Q0656 MD 0/2 5 2 4 B5 100/66 Q0657 VR,MD 0/2 5 2 4 B5 100/66 Q0658 VRE,MD 0/2 5 2 4 B5 120/60 Q0707 VRE,MD,#1 0/2 5 2 4 B5 120/60 Q0708 STD,#1 0/2 5 2 4 B5 75/50 SX975 TCP 0/2 5 2 4 B5 75/50 SX961 STD 0/2 5 2 4 B5 75/50 SZ977 STD,#5 0/2 5 2 4 B5 90/60 SX957 STD 0/2 5 2 4 B5 90/60 SX958 VR 0/2 5 2 4 B5 90/60 SX959 MD 0/2 5 2 4 B5 90/60 SZ978 STD,#5 0/2 5 2 4 B5 100/66 SX962 VRE,MD 0/2 5 2 5 C2 75/50 Q0725 TCP 0/2 5 2 5 C2 75/50 Q0700 STD 0/2 5 2 5 C2 75/50 Q0749 MD 0/2 5 2 5 C2 90/60 Q0699 STD 0/2 5 2 5 C2 100/50,66 Q0698 VRE,MD 0/2 5 2 5 C2 100/50,66 Q0697 STD 0/2 5 2 5 C2 120/60 Q0711 VRE,MD 0/2 5 2 5 C2 120/60 Q0732 VRE,MD 0/2 5 2 5 C2 133/66 Q0733 MD 0/2 5 2 5 C2 133/66 Q0751 MD 0/2 5 2 5 C2 133/66 Q0775 VRE,MD 0/2 5 2 5 C2 75/50 SK079 TCP 0/2 5 2 5 C2 75/50 SX969 STD 0/2 5 2 5 C2 75/50 SX998 MD 0/2 5 2 5 C2 75/50 SZ994 STD,#5 0/2 5 2 5 C2 75/50 SU070 STD,#6 0/2 5 2 5 C2 90/60 SX968 STD 0/2 5 2 5 C2 90/60 SZ995 STD,#5 0/2 5 2 5 C2 90/60 SU031 STD,#6 0/2 5 2 5 C2 100/50,66 SX970 VRE,MD 0/2 5 2 5 C2 100/50,66 SX963 STD 0/2 5 2 5 C2 100/50,66 SZ996 STD,#5 0/2 5 2 5 C2 100/66,50 SU032 STD,#6 0/2 5 2 5 C2 120/60 SK086 VRE,MD 0/2 5 2 5 C2 120/60 SX994 VRE,MD 0/2 5 2 5 C2 120/60 SU033 VRE,MD,#6 0/2 5 2 5 C2 133/66 SK098 MD 0/2 5 2 5 C2 133/66 SK103 VRE,MD 0 5 2 5 mA1 75/50 Q0686 VRT,TCP,#4 0 5 2 5 mA1 75/50 Q0689 VRT,SPGA,#4 0 5 2 5 mA1 90/60 Q0694 VRT,TCP,#4 0 5 2 5 mA1 90/60 Q0695 VRT,SPGA,#4 0 5 2 5 mA1 75/50 SK089 VRT,TCP,#4 0 5 2 5 mA1 75/50 SK091 VRT,SPGA,#4 0 5 2 5 mA1 90/60 SK090 VRT,TCP,#4 0 5 2 5 mA1 90/60 SK092 VRT,SPGA,#4 0/2 5 2 B cB1 120/60 Q0776 STD,no kit,#3,#4 0/2 5 2 B cB1 133/66 Q0772 STD,no kit,#3,#4 0/2 5 2 B cB1 133/66 Q0773 STD,#4 0/2 5 2 B cB1 133/66 Q0774 VRE,MD,no kit,#3,#4 0/2 5 2 B cB1 120/60 SK110 STD,no kit,#3,#4 0/2 5 2 B cB1 133/66 SK106 STD,no kit,#3,#4 0/2 5 2 B cB1 133/66 SK106J STD,no kit,#3,#4,#7 0/2 5 2 B cB1 133/66 SK107 STD,#4 0/2 5 2 B cB1 133/66 SU038 STD,no kit,#3,#4,#6 0 5 2 B mcB1 100/66 Q0884 VRT,TCP 0 5 2 B mcB1 120/60 Q0779 VRT,TCP,#4 0 5 2 B mcB1 120/60 Q0808 3.3V,SPGA,#4 0 5 2 B mcB1 100/66 SY029 VRT,TCP 0 5 2 B mcB1 120/60 SK113 VRT,TCP,#4 0 5 2 B mcB1 120/60 SK118 VRT,TCP,#4,#7 0 5 2 B mcB1 120/60 SX999 3.3V,SPGA,#4 0/2 5 2 C cC0 150/60 Q0835 STD 0/2 5 2 C cC0 166/66 Q0836 VRE,no kit,#3 0/2 5 2 C cC0 166/66 Q0841 VRE/STD 0/2 5 2 C cC0 150/60 SY015 STD 0/2 5 2 C cC0 150/60 SU071 STD,#6 0/2 5 2 C cC0 166/66 SY016 VRE,no kit,#3 0/2 5 2 C cC0 166/66 SY017 VRE/STD 0/2 5 2 C cC0 166/66 SU072 VRE,no kit,#3,#6 0 5 7 0 mA4 75/50 Q0848 VRT,TCP,#4 0 5 7 0 mA4 75/50 Q0851 VRT,SPGA,#4 0 5 7 0 mA4 90/60 Q0849 VRT,TCP,#4 0 5 7 0 mA4 90/60 Q0852 VRT,SPGA 0 5 7 0 mA4 100/66 Q0850 VRT,TCP,#4 0 5 7 0 mA4 100/66 Q0853 VRT,SPGA,#4 0 5 7 0 mA4 75/50 SK119 VRT,TCP,#4 0 5 7 0 mA4 75/50 SK122 VRT,SPGA,#4 0 5 7 0 mA4 90/60 SK120 VRT,TCP,#4 0 5 7 0 mA4 90/60 SK123 VRT,SPGA,#4 0 5 7 0 mA4 100/66 SK121 VRT,TCP,#4 0 5 7 0 mA4 100/66 SK124 VRT,SPGA,#4 Notes: STD = Vcc=3.135-3.465V DP = dual processor VR = Vcc=3.300-3.465V MD = modified timing VRE = Vcc=3.450-3.600V ES = engineering sample VRT = Intel's Voltage Reduction Technology. Vcc for I/O is 3.3V, core Vcc (accounting for about 90% of power usage) is reduced to 2.9V, to reduce power consumption and heating TCP = TCP package SPGA = SPGA package #1 = Tcase max. 60øC #2 = this part uses VRT #3 = that part meets the EDS specifications but is not tested to support the 82498/82493 and 82497/82492 cache timings #4 = cB1 stepping is logically equivalent to the C2 step, but on a different manufacturing process; mcB1 stepping is logically equivalent to the cB1 step (except it does not support DP, APIC or FRC); mcB1 and mA1 and mA4 step use VRT, and are available in the TCP and SPGA package, primarily to support mobile applications; "m" prefix, for "mobile" #5 = boxed iPentium processor without the attached fan heatsink #6 = boxed iPentium processor with an attached fan heatsink #7 = this part does not support boundary scan Intel iPentium OverDrive P24T processor: type family model step mask clock SX-no Vcc øC notes 1 5 3 1 B1 63/25 SZ953 N/A N/A version 1.0 1 5 3 1 B2 63/25 SZ990 N/A N/A version 1.1 1 5 3 2 C0 83/33 SU014 N/A N/A version 2.1 Intel iPentiumPro P6 processor: type family model step mask clock SX-no Vcc øC notes 0 6 1 1 B0 150/60 SY002 3.1V 0-85 #1 0 6 1 1 B0 150/60 SY011 3.1V 0-85 0 6 1 1 B0 150/60 SY014 3.1V 0-85 0 6 1 2 C0 150/60 SY010 3.1V 0-85 0 6 1 6 sA0 180/60 SY012 3.3V 0-85 #2 0 6 1 6 sA0 200/66 SY013 3.3V 0-85 #2 0 6 1 6 sA0 166/60 SY024 3.3V 0-85 #2,#3 0 6 1 6 sA0 200/66 SY025 3.3V 0-85 #2,#3 0 6 1 7 sA1 200/66 SY031 3.3V 0-85 0 6 1 7 sA1 180/60 SY032 3.3V 0-85 Notes: #1 = The VID pins are not supported on these parts. #2 = The sA0 stepping is logically equivalent to the C0 stepping (shrinked). #3 = These parts are equipped with a 512KB L2 cache.